This invention relates generally to a method for forming a thin coating of gold on a copper base via electroless deposition, and more particularly to such a method for electroless gold deposition on a copper base which was formed by an additive process using a palladium seeder to initiate formation of the copper base.
As electronic circuit packaging performance increases, the demand for higher wiring and component density also increases. To meet the higher density requirements, surface mount technology (SMT), such as flip chip attach (FCA), direct chip attach (DCA), ball grid array(BGA), and similar technology is required. In most cases, the copper interconnecting pads have to be contamination and oxidation free to achieve adequate wetability.
In order to achieve adequate wetting and prevent corrosion of the copper pads during application of conductive epoxy, it is necessary to deposit a thin gold overlay onto the copper base. Typically, a thin nickel interlayer is required between the copper and gold overlay to assure adequate bonding of the gold overlay to the underlying copper surface. However, when the circuit features on the substrates are fabricated by the full additive process, conventional electroless gold deposition causes bridging between the lines and/or pads defining the electrical circuit features on the substrate, that may be spaced apart on the order of about 2 mil or less. The fully additive process used to define the copper features relies on having a palladium catalyst on the surface to be plated. This is provided by seeding the surface with a suitable palladium seeder such as palladium chloride. Heretofore, if the primary catalyst is not removed prior to gold conformal plating, gold will plate on the substrate and form shorts bridging between the conductive copper features. It is very difficult to remove the plating seed layer from between closely spaced electrically conductive features.
The present invention is directed to overcoming the problems set forth above. It is desirable to have an effective gold deposition process by which gold may be directly deposited on the exposed surface of previously defined closely spaced copper electronic circuit features, without the need for a nickel surface, and which avoids bridging of gold between conductive circuit features. It is also desirable to have an economical process for forming a thin gold coating on previously defined closely spaced copper circuit features formed by the fully additive process, which does not require removal of the palladium seeder prior to deposition of the gold coating.
In accordance with one aspect of the present invention, a method for electroless gold deposition in the presence of a palladium seeder includes providing a substrate having copper circuit features that were formed on the substrate by a full additive process employing a palladium catalyst to initiate the formation of the copper circuit features on the substrate. The substrate is treated with an alkaline cleaner, rinsed, and then treated with sodium persulfate, again rinsed, and treated with dilute sulfuric acid. After treatment with the sulfuric acid, the substrate is again rinsed and then immersed in a gold deposition solution. After immersion of the substrate in the gold deposition solution, whereby gold is deposited on the exposed surfaces of the copper circuit features disposed on the substrate, the substrate is rinsed and dried.
Other features of the method for electroless gold deposition in the presence of a palladium seeder, in accordance with the present invention, includes carrying out the steps of treating the substrate with an alkaline cleaner, with sodium persulfate, and diluted sulfuric acid, by immersion in a respective bath containing said materials for a period of about one minute. Other features include, in the subsequently carried out steps of rinsing after each of the above described treatments, rinsing the substrate in a flowing stream of deionized water for about two minutes. Still other features include heating the gold deposition solution to a temperature of about 85xc2x0 C. and immersing the substrate in the solution for about 10 to 15 minutes, or alternatively, for a period of time sufficient to form a gold coating having a thickness of from about 5,000 xc3x85 to about 15,000 xc3x85.
In accordance with another aspect of the present invention, an electronic circuit board has a dielectric substrate and a plurality of electric circuit features formed on the substrate. The copper circuit features are formed by an additive process in which sharply defined edges are formed between substantially planar surfaces and sides of the features by using a catalyst material having palladium as a primary component to initiate the formation of the copper circuit features on the substrate. The electronic circuit board has detectable amounts of the palladium catalyst on the sides of the copper circuit features over which a layer of gold is conformally deposited, in direct contact with the surface and sides of the copper circuit features.
Other features include the layer of gold having a thickness of from about 5,000 xc3x85 to about 15,000 xc3x85. The electronic circuit board is further characterized by the absence of a gold interlayer between the copper circuit features and the gold layer.